Operational amplifier circuit capable of improving linearity relation between loading current and input voltage difference

ABSTRACT

An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.

This application is a continuation-in-part application of co-pendingapplication Ser. No. 15/716,789, filed on Sep. 27, 2017, which claimsthe benefit of U.S. provisional application Ser. No. 62/508,457, filedon May 19, 2017, the contents of which are incorporated herein byreference.

TECHNICAL FIELD

The disclosure relates in general to an operational amplifier circuit,and more particularly to an operational amplifier circuit capable ofimproving linearity relation between the loading current and the inputvoltage difference of the differential input stage circuit.

BACKGROUND

An operational amplifier circuit has a variety of applications in modernelectronic devices. For example, the operational amplifier circuit maybe used in a driver circuit for driving a display panel, such as aliquid crystal display (LCD) panel. It is common for an operationalamplifier to adopt a differential pair as an input stage for receivinginput signals. The linear range of the differential pair is affected bythe input voltage difference of the differential pair. For example, therelation between the input voltage difference and the loading current(such as the drain current in a MOSFET implemented differential pair) islinear when the input voltage difference is small. However, the relationbecomes nonlinear when the input voltage difference is too large. Inorder to increase the linear range, a known approach is to providelarger bias current for the differential pair, which in turn results inlarger power consumption.

FIG. 1 shows a block diagram of an example operational amplifier. Theoperational amplifier (OP) circuit 10 includes a differential inputstage circuit 111, a loading stage circuit 112, and an output stagecircuit 131. The differential input stage circuit 111 receives a pair ofdifferential signals including the first input signal V_(in1) and thesecond input signal V_(in2). The differential input stage circuit 111may be configured to convert a voltage difference between the firstinput signal V_(in1) and the second input signal V_(in2) to loadingcurrents i₁, i₂. The loading stage circuit 112 may be configured toconvert the loading currents i₁, i₂ outputted by the differential inputstage circuit 111 to an output signal V_(O). The loading stage circuit112 may include an active load circuit (such as transistors) and/or apassive load circuit (such as resistors, capacitors, and inductors). Theloading stage circuit 112 may also be referred as a gain stage circuit.

The combination of the differential input stage circuit 111 and theloading stage circuit 112 may be referred as the 1^(st) stage OP 11,whose output is defined as a first stage output V_(O1). The output stagecircuit 131 may be referred as the 2^(nd) stage OP 13, whose output isdefined as a second stage output V_(O2). The voltage gain A_(v) of theoperational amplifier circuit 10 is the product of the voltage gainA_(v1) of the 1^(st) stage OP 11 and the voltage gain A_(v2) of the2^(nd) stage OP 12 (A_(v)=A_(v1)×A_(v2)). The voltage gain A_(v1) of the1^(st) stage OP 11 is the transconductance Gm of the differential inputstage circuit 111 multiplied by the output resistance r_(o) of theloading stage circuit 102 (A_(v1)=Gm×r_(o)).

The second stage output V_(O2) provided by the output stage circuit 131is a single-ended voltage signal. If the operational amplifier circuit10 is used in a display device, the output stage circuit 131 may becoupled to a display panel. It should be noted that number of Ops beingincluded in the operational amplifier circuit 10 is not limited, andoutput of the last stage of the Ops in the operational amplifier circuit10 is utilized as an output signal Vout. In the example shown in FIG. 1,the operational amplifier circuit 10 includes two stages of OP. In otherembodiments, there may be only one stage OP or more than two stages ofOP. Because the 2^(nd) stage OP (as well as other 3^(rd), 4^(th) . . .stage OP) is optional, the main focus in the following description willbe on the 1^(st) stage OP 11, including the differential input stagecircuit 111 and the loading stage circuit 112.

FIG. 2A shows a circuit diagram of an example differential input stagecircuit. In this example, the differential input stage circuit 111 ofthe operational amplifier circuit 10 includes two n-typemetal-oxide-semiconductor field-effect transistor (NMOS) transistors M01and M02 and a current source Iss. The current source Iss is coupled to aground terminal Gnd. The two NMOS transistor Min1 and Min2 have equalgate width and equal gate length. The current value provided by thecurrent source Iss is I. Transistor Min1 receives the first input signalV_(in1), and transistor Min2 receives the second input signal V_(in2).Being defined as input transistors, transistors Min1 and Min2 in thedifferential input stage circuit 111 operate in the saturation region.

In order to discuss the operation of the input transistors Min1 andMin2, two types of linearity enhancement circuit are provided in thepresent disclosure, namely, a bias control circuit and a voltagemaintaining circuit. Basically, the bias control circuit is used toreduce the variance range of the loading current being affected byvariance of the coupled in between the current source and an inputcircuit, and the voltage maintaining circuit is coupled in between theloading stage circuit and the input circuit.

The loading currents i₁ and i₂ flowing through these two inputtransistors Min1 and Min2 may be represented by the following formulas:

$\begin{matrix}{i_{1} = {\frac{1}{2} + {\sqrt{\mu_{n}C_{ox}\frac{W}{L}I_{SS}}\left( \frac{\Delta \; v_{in}}{2} \right)\sqrt{1 - \frac{\left( {\Delta \; {v_{in}/2}} \right)^{2}}{{I/\mu_{n}}C_{ox}\frac{W}{L}}}}}} & \left( {{{Eq}.\mspace{14mu} 1}A} \right) \\{i_{2} = {\frac{1}{2} - {\sqrt{\mu_{n}C_{ox}\frac{W}{L}I_{SS}}\left( \frac{\Delta \; v_{in}}{2} \right)\sqrt{1 - \frac{\left( {\Delta \; {v_{in}/2}} \right)^{2}}{{I/\mu_{n}}C_{ox}\frac{W}{L}}}}}} & \left( {{{Eq}.\mspace{14mu} 1}B} \right)\end{matrix}$

where μ_(n) is the charge-carrier effective mobility, W is the gatewidth of the NMOS transistor Min1, L is the gate length of the NMOStransistor Min1, C_(ox) is the gate oxide capacitance per unit area, andΔv_(in) is the input voltage difference, Δv_(in)=V_(in1)−V_(in2). Basedon Eq. 1A and Eq. 1B, when

$\begin{matrix}{{\frac{v_{id}}{2}\sqrt{\frac{1}{\mu_{n}C_{ox}\frac{W}{L}}}},} & \left( {{Eq}.\mspace{14mu} 2} \right)\end{matrix}$

the loading currents i₁ and i₂ may be approximately represented as alinear relation as follows:

$\begin{matrix}{i_{1} = {\frac{I}{2} + {\sqrt{\mu_{n}C_{ox}\frac{W}{L}I_{SS}}\left( \frac{\Delta \; v_{in}}{2} \right)}}} & \left( {{{Eq}.\mspace{14mu} 3}A} \right) \\{i_{2} = {\frac{I}{2} - {\sqrt{\mu_{n}C_{ox}\frac{W}{L}I_{SS}}\left( \frac{\Delta \; v_{in}}{2} \right)}}} & \left( {{{Eq}.\mspace{14mu} 3}B} \right)\end{matrix}$

That is, when the condition in Eq. 2 is satisfied, the relation betweenthe loading currents i₁, i₂ and the input voltage difference ΔV_(in) islinear. The transconductance Gm of the differential pair shown in FIG.2A is:

$\begin{matrix}{G_{m} = {\frac{i_{1}}{\Delta \; {v_{in}/2}} = \sqrt{\mu_{n}C_{ox}\frac{W}{L}I_{SS}}}} & \left( {{Eq}.\mspace{14mu} 4} \right)\end{matrix}$

Although the above analyses are based on the operation of thedifferential input pair having NMOS transistors, analyses for thedifferential input pair having PMOS transistors are similar and notredundantly illustrated.

FIG. 2B shows a diagram illustrating a transconductance of thedifferential input stage circuit shown in FIG. 2A. The horizontal axisis the input voltage difference ΔV_(in). The transconductance Gm isrelatively stable when the input voltage difference ΔV_(in) is small,and hence there is a linear transfer relation between the loadingcurrents i₁, i₂ and the input voltage difference ΔV_(in). When the inputvoltage difference ΔV_(in) becomes larger, the transconductance Gmdecreases, and the transfer relation becomes nonlinear. When the inputvoltage difference ΔV_(in), exceeds +ΔV1 (or less than −ΔV1), thetransconductance Gm becomes 0, and hence the differential pair does notworker properly under such input voltage condition.

Normally, the input transistors Min1, Min2 are desired to operate in thesaturation region. For transistors operate in the saturation region,whose drain current and gate-source voltage Vgs are non-linear. Underthe circumstance that channel length modulation effect can be neglected,the drain currents of the input transistor Min1 and the second inputtransistor Min2 and the input voltage difference ΔV_(in) can berepresented by Eq. 5. In FIG. 2, the drain currents of the first inputtransistor Min1 and the input transistor Min2 are equivalent to theloading currents i₁, and i₂, respectively.

$\begin{matrix}{{\Delta \; V_{i\; n}} = {{V_{i\; n\; 1} - V_{i\; n\; 2}} = {\sqrt{\frac{2i_{1}}{\mu_{n}C_{ox}\frac{W}{L}}} - \sqrt{\frac{2i_{2}}{\mu_{n}C_{ox}\frac{W}{L}}}}}} & \left( {{Eq}.\mspace{14mu} 5} \right)\end{matrix}$

After formula manipulation and simplification, Eq. 5 can be representedas Eq. 6.

$\begin{matrix}{{{\frac{1}{2}\mu_{n}C_{ox}\frac{W}{L}\left( {V_{i\; n\; 1} - V_{i\; n\; 2}} \right)^{2}} - I_{SS}} = {{- 2}\sqrt{i_{1}i_{2}}}} & \left( {{Eq}.\mspace{14mu} 6} \right)\end{matrix}$

In Eq. 6, the source current Iss is equivalent to summation of theloading currents i₁ and i₂, that is, (Iss=I₁+I₂). After formulamanipulation and simplification, that is, putting square on both side ofEq. 6 and representing the source current Iss with the loading currentsi₁ and i₂, Eq. 6 can be further conducted to obtain Eq. 7.

$\begin{matrix}{{i_{1} - i_{2}} = {\frac{1}{2}\mu_{n}C_{ox}\frac{W}{L}\left( {V_{i\; n\; 1} - V_{i\; n\; 2}} \right)\sqrt{\frac{4I_{SS}}{\mu_{n}C_{ox}\frac{W}{L}} - \left( {V_{i\; n\; 1} - V_{i\; n\; 2}} \right)^{2}}}} & \left( {{Eq}.\mspace{14mu} 7} \right)\end{matrix}$

As i₁−i₂=ΔI_(D), V_(in1)−V_(in2)=ΔV_(in), the relations between theloading currents i₁, i₂ and the input voltage difference ΔV_(in) can beobtained, which is shown in FIG. 2C. Moreover, the transconductance (Gm)of the differential input pair is equivalent to calculating thedifferential of the loading current difference (ΔI_(D)=i₁−i₂) to theinput voltage difference ΔV_(in).

$\begin{matrix}{G_{m} = {\frac{{\partial\Delta}\; I_{D}}{{\partial\Delta}\; V_{i\; n}} = {\frac{1}{2}\mu_{n}C_{ox}\frac{W}{L}\frac{\frac{4I_{SS}}{\mu_{n}C_{ox}\frac{W}{L}} - {2\; \Delta \; V_{i\; n}^{2}}}{\sqrt{\frac{4I_{SS}}{\mu_{n}C_{ox}\frac{W}{L}} - {\Delta \; V_{i\; n}^{2}}}}}}} & \left( {{Eq}.\mspace{14mu} 8} \right)\end{matrix}$

When the input voltage difference ΔV_(in) is small,

${\Delta \; V_{i\; n}}\sqrt{\frac{2I_{SS}}{\mu_{n}C_{ox}\frac{W}{L}}}$

is satisfied. Meanwhile, the transconductance (Gm) of the differentialinput pair can be represented as Eq. 9.

$\begin{matrix}{G_{m} = \sqrt{\mu_{n}C_{ox}\frac{W}{L}I_{ss}}} & \left( {{Eq}.\mspace{14mu} 9} \right)\end{matrix}$

According to Eq. 9, when the input voltage difference is small, relationbetween the loading currents i₁, i₂ and the input voltage differenceΔV_(in) are linear. However, with increment of the input voltagedifference ΔV_(in), Eq. 8 can no longer be conducted to Eq. 9.Therefore, linearity between the loading currents i₁, i₂ and the inputvoltage difference becomes worse. Furthermore, since the current of thecurrent source Iss starts to gather at one of the input transistorsMin1, Min2, the transconductance Gm becomes to decrease. In a case thatthe absolute value of the input voltage difference ΔV_(in) is greaterthan ΔV1, all the current originating from the current source Isssimultaneously flow to one of the input transistors Min1, Min2, and thedifferential input pair cannot operate normally, that is, Gm=0. Althoughthe above analyses are based on the operation of the differential inputpair having NMOS transistors, analyses for the differential input pairhaving PMOS transistors can be analogue and not illustrated to avoidredundancy.

FIG. 2C shows a diagram illustrating a relation between the loadingcurrents versus input voltage difference of the differential input stagecircuit shown in FIG. 2A. The vertical axis represents the loadingcurrent i₁, i₂ and the horizontal axis represents the input voltagedifference ΔV_(in).

In FIG. 2C, curve Ci1 and curve Ci2 represent the relation between thefirst and the second loading currents i₁, i₂ and the input voltagedifference ΔV_(in), respectively. As shown by the curve Ci1, when theinput voltage difference ΔV_(in) is in a relatively small range, thefirst loading current i₁ is relatively proportional to the input voltagedifference ΔV_(in) and there is a linear transfer relation betweenvariance of the first loading current Δi₁ and the input voltagedifference ΔV_(in). As shown by the curve Ci2, when the input voltagedifference ΔV_(in) is in a relatively small range, the second loadingcurrent i₂ is relatively inversely proportional to the input voltagedifference ΔV_(in) and there is a negative linear transfer relationbetween variance of the second loading current Δi₂ and the input voltagedifference ΔV_(in).

Alternatively speaking, when the input voltage difference input voltagedifference ΔV_(in) becomes larger, the variance degrees of the firstloading current i₁ and the second loading current i₂ decreases, and thetransfer relations between the loading currents (i₁ and i₂) are nolonger proportional or inversely proportional to the input voltagedifference ΔV_(in). When the input voltage difference ΔV_(in) exceeds+ΔV1 (or less than −ΔV1), the first loading current i₁ and the secondloading current i2 basically remain constant, and hence the differentialpair does not work properly under such input voltage condition.

The linear range of a differential pair is especially important for theoperational amplifier circuit in a LCD driver circuit. When the inputvoltage difference of the differential pair exceeds the linear range,the output signal may deviate from the desired value, and hence theimage quality provided by the LCD panel is degraded. Therefore, it is animportant subject in the industry to design an operational amplifiercircuit with extended linear range.

SUMMARY

The disclosure is directed to an operational amplifier circuit and adifferential input stage circuit having a linearity enhancement circuitso that the differential input stage can achieve a larger linear range.

According to one embodiment of the invention, an operational amplifiercircuit is provided. The operational amplifier circuit includes adifferential input stage circuit and a loading stage circuit. Thedifferential input stage circuit includes a first input circuit, a firstvoltage maintaining circuit and a first current source. The first inputcircuit further includes a first input transistor and a second inputtransistor. The first input transistor has a first terminal, a secondterminal, and a control terminal for receiving a first input signal, andthe second input transistor has a first terminal, a second terminal, anda control terminal for receiving a second input signal. The firstvoltage maintaining circuit includes a first branch circuit and a secondbranch circuit. The first branch circuit is coupled to the firstterminal and the control terminal of the first input transistor, forreceiving the first input signal. The second branch circuit is coupledto the first terminal and the control terminal of the second inputtransistor, for receiving the second input signal. The first currentsource is coupled to the second terminals of the first input transistorand the second input transistor. The loading stage circuit is coupled tothe first voltage maintaining circuit, for generating a first stageoutput.

The invention will become apparent from the following detaileddescription of the preferred but non-limiting embodiments. The followingdescription is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (prior art) shows a block diagram of an example operationalamplifier.

FIG. 2A (prior art) shows a circuit diagram of an example differentialinput stage circuit.

FIG. 2B (prior art) shows a diagram illustrating a transconductance ofthe differential input stage circuit shown in FIG. 2A.

FIG. 2C (prior art) shows a diagram illustrating a relation betweenloading currents versus input voltage difference of the differentialinput stage circuit shown in FIG. 2A.

FIG. 3A shows an operational amplifier circuit having a linearityenhancement circuit according to one embodiment of the invention.

FIG. 3B is a schematic diagram illustrating a bias control circuit isused as the linearity enhancement circuit according to an embodiment ofthe invention.

FIG. 3C is a schematic diagram illustrating a voltage maintainingcircuit is used as the linearity enhancement circuit according toanother embodiment of the invention.

FIG. 4A shows an operational amplifier circuit having a bias controlcircuit and an NMOS differential pair according to an embodiment of theinvention.

FIG. 4B shows a diagram illustrating a transconductance of thedifferential input stage circuit shown in FIG. 4A.

FIG. 5 shows an operational amplifier circuit having a bias controlcircuit and a PMOS differential pair according to an embodiment of theinvention.

FIG. 6 shows a rail-to-rail operational amplifier circuit having biascontrol circuits according to an embodiment of the invention.

FIG. 7 shows an example implementation of the loading stage circuit andthe output stage circuit together with the rail-to-rail architectureshown in FIG. 6.

FIG. 8A shows an operational amplifier circuit having a voltagemaintaining circuit and an NMOS differential pair according to anembodiment of the invention.

FIG. 8B shows a diagram illustrating the loading currents versus inputvoltage difference of the differential input stage circuit shown in FIG.8A.

FIG. 9 shows an operational amplifier circuit having a voltagemaintaining circuit and a PMOS differential pair according to anembodiment of the invention.

FIG. 10 shows a rail-to-rail operational amplifier circuit havingvoltage maintaining circuits according to an embodiment of theinvention.

FIG. 11 shows an example implementation of the loading stage circuit andthe output stage circuit together with the rail-to-rail architectureshown in FIG. 10.

FIG. 12 shows an operational amplifier circuit having a voltagemaintaining circuit and an NMOS differential pair according to anotherembodiment of the invention.

FIG. 13 shows an operational amplifier circuit having a voltagemaintaining circuit and a PMOS differential pair according to anotherembodiment of the invention.

FIG. 14 shows a rail-to-rail operational amplifier circuit havingvoltage maintaining circuits according to another embodiment of theinvention.

FIG. 15 shows an example implementation of the loading stage circuit andthe output stage circuit together with the rail-to-rail architectureshown in FIG. 14.

FIG. 16 shows an operational amplifier circuit including multipledifferential pairs according to one embodiment of the invention.

FIG. 17A shows a differential input stage circuit with voltageinterpolation function according to one embodiment of the invention.

FIG. 17B shows the voltage levels of signals shown in FIG. 17A.

FIG. 18A shows a differential input stage circuit with voltageinterpolation function according to one embodiment of the invention.

FIG. 18B shows the voltage levels of signals shown in FIG. 18A.

FIG. 19A shows a differential input stage circuit with voltageinterpolation function according to another embodiment of the invention.

FIG. 19B shows the voltage levels of signals shown in FIG. 19A.

In the following detailed description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of the disclosed embodiments. It will be apparent,however, that one or more embodiments may be practiced without thesespecific details. In other instances, well-known structures and devicesare schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

FIG. 3A shows an operational amplifier circuit having a linearityenhancement circuit according to one embodiment of the invention. Theoperational amplifier circuit 20 includes a differential input stagecircuit 211, a loading stage circuit 212 and an output stage circuit231. In addition to an input circuit 211 a for receiving the first inputsignal V_(in1) and the second input signal V_(in2) and a current source211 c, the differential input stage circuit 211 according to anembodiment of the present disclosure further includes a linearityenhancement circuit 211 b being coupled to the input circuit 211 a.

According to an embodiment of the present disclosure, one of the inputcircuit 211 a and the linearity enhancement circuit 211 b is coupled tothe loading stage circuit 212 through a first loading terminal Nld1 anda second loading terminal Nld2, and the other of the input circuit 211 aand the linearity enhancement circuit 211 b is coupled to the currentsource 211 c.

The linearity enhancement circuit 211 b can be implemented in differentmanner, for example, a bias control circuit, a voltage maintainingcircuit and so forth. More details regarding implementation of the biascontrol circuit and the voltage maintaining circuit are used areillustrated below.

The operational amplifier circuit 20 may be used in a display device.For example, the output terminal of the loading stage circuit 212 may becoupled to an output stage circuit 231. The output stage circuit 31 mayinclude power MOSFETs to provide sufficient driving capability. In oneembodiment, the output stage circuit 231 is configured to provide asingle-ended voltage signal (second stage output V_(O2)) for driving adisplay panel.

FIG. 3B is a schematic diagram illustrating a bias control circuit isused as the linearity enhancement circuit according to an embodiment ofthe invention. In a case that the linearity enhancement circuit 211 b isa bias control circuit 251 b, the input circuit 251 a is coupled to thefirst loading terminal Nld1 and the second loading terminal Nld2, andthe bias control circuit 251 b is coupled to the current source 251 c.FIGS. 4A, 4B, 5, 6 and 7 are schematic diagrams related to theembodiment that the differential input stage includes the bias controlcircuit.

FIG. 3C is a schematic diagram illustrating a voltage maintainingcircuit is used as the linearity enhancement circuit according toanother embodiment of the invention. In a case that the linearityenhancement circuit 211 b is a voltage maintaining circuit 281 b, thevoltage maintaining circuit 281 b is coupled to the first loadingterminal Nld1 and the second loading terminal Nld2, and the inputcircuit 281 a is coupled to the current source 281 c. Moreover, both theinput circuit 281 b and the input circuit 281 a receive the first inputsignal V_(in1) and the second input signal V_(in2).

As shown in FIG. 3C, the voltage maintaining circuit 281 b furtherincludes a first branch circuit 282 and a second branch circuit 283. Thefirst branch circuit 282 receives the first input signal V_(in1) andgenerates the first loading current i₁; and the second branch circuit283 receives the second input signal V_(in2) and generates the secondloading current i₂. FIGS. 8A, 8B, 9, 10, 11 are schematic diagramsshowing that the differential input stage includes a first type of thevoltage maintaining circuit, and FIGS. 12, 13, 14 and 15 are diagramsshowing that the differential input stage includes a second type of thevoltage maintaining circuit.

In the following embodiments, PMOS transistors and NMOS transistors areused for illustration purpose. In practical applications, NMOStransistors may be replaced by NPN-type BJTs, and PMOS transistors maybe replaced by PNP-type BJTs. In still another embodiment, other typesof transistors such as junction gate field-effect transistor (JFET) maybe used instead, or different types of transistors may be used incombination in one differential pair.

FIG. 4A shows an operational amplifier circuit having a bias controlcircuit and an NMOS differential pair according to an embodiment of theinvention. The operational amplifier circuit 30 includes a differentialinput stage circuit 301 and a loading stage circuit 302. Thedifferential input stage circuit 101 includes a current source I_(N), aninput circuit 301 a and a bias control circuit 301 b. The input circuit301 a further includes input transistors Min1, Min2, and the biascontrol circuit 301 b further includes transistors Mb1 and Mb2.

The control terminal of the input transistor Min1 receives a first inputsignal V_(in1). The control terminal of the input transistor Min2receives a second input signal V_(in2). The first and the second inputsignals V_(in1), V_(in2) jointly form a pair of differential signal.Transistor Mb1 has a first terminal coupled to the second terminal ofthe input transistor Min1, a second terminal coupled to the currentsource I_(N), and a control terminal coupled to the control terminal oftransistor Min2. Transistor Mb2 has a first terminal coupled to thesecond terminal of transistor Min2, a second terminal coupled to thecurrent source I_(N), and a control terminal coupled to the controlterminal of the input transistor Min1. The loading stage circuit 302 iscoupled to the first terminal of the input transistor Min1 and the firstterminal of the input transistor Min2, for generating an output signalV_(O) at an output terminal of the operational amplifier circuit 11 b.

In the example shown in FIG. 4A, transistors Min1, Min2, Mb1 and Mb2 areNMOS transistors. The first terminal, the second terminal, and thecontrol terminal of an NMOS transistor may correspond to the drainterminal, the source terminal, and the gate terminal, respectively.

In one embodiment, the sizes (gate width W and gate length L) of theinput transistors Min1 and Min2 are substantially equal (represented as

$\left( \frac{W}{L} \right)_{1}$

in the following formulas). The sizes of transistors Mb1 and Mb2 aresubstantially equal (represented as

$\left( \frac{W}{L} \right)_{3}$

in the following formulas).

As can be seen in FIG. 4A, the bias voltage of transistor Mb1 is avariable voltage. Similarly, the bias voltage of transistor Mb2 is alsoa variable voltage. The differential pair shown in FIG. 4 uses avariable bias control mechanism. In this circuit, the input transistorsMin1 and Min2 operate in the saturation region. Transistors Mb1 and Mb2operate in the triode region, acting as variable resistors. TransistorsMb1 and Mb2 are degeneration devices for the input transistors Min1 andMin2 respectively. Transistors Mb1 and Mb2 constitute a feedback loop atthe second terminal (source terminal) of the input transistors Min1 andMin2, effectively extending the linear range of the operationalamplifier circuit 301.

Refer to FIG. 4A, when the input voltage difference ΔV_(in)(ΔV_(in)=V_(in1)−V_(in2)) is small, transistors Mb1 and Mb2 operate inthe triode region. Taking transistor Mb1 for example, the resistancevalue between its drain terminal and its source terminal is controlledby the second input signal V_(in2). Similarly, the resistance valuebetween the drain terminal and the source terminal of transistor Mb2 iscontrolled by the first input signal V_(in1). Consider the situationwhen the voltage of the first input signal V_(in1) increases and thevoltage of the second input signal V_(in2) decreases, the loadingcurrent i₁ will increase, and the loading current i₂ will decrease.Because the resistance value between the drain terminal and the sourceterminal of transistor Mb1 increases (caused by decreased V_(in2)), theincreased loading current i₁ will increase the voltage across the drainterminal and the source terminal of transistor Mb1. Because of suchnegative feedback, the increment (the amount that the voltage increases)of the gate-to-source voltage of the input transistor Min1 will besmaller than the increment of the first input signal V_(in1). Therefore,the increment of the loading current i₁ decreases. On the other hand,the resistance value between the drain terminal and the source terminalof the input transistor Mb2 decreases (caused by increased V_(in1)), thedecreased loading current i₂ will decrease the voltage across the drainterminal and the source terminal of transistor Mb2. The decrement of thegate-to-source voltage of transistor Min2 will be smaller than thedecrement of the second input signal V_(in2). Therefore, the loadingcurrent i₂ will not decrease rapidly. As described above, when thevoltage of the first input signal V_(in1) increases and the voltage ofthe second input signal V_(in2) decreases, the change in the loadingcurrents i₁ and i₂ can be kept small, resulting in an improved linearrange for the differential pair. The detailed analyses for current andvoltage of the circuit shown in FIG. 4A are provided below.

Loading current i₁ being calculated by current flowing throughtransistor Min1:

i ₁=½k ₁(V _(in1) −V _(S1) −V _(t1))²

Loading current i₁ being calculated by current flowing throughtransistor Mb1:

i ₁ =k ₃(V _(in2) −V _(S) −V _(t3))(V _(S1) −V _(S))

Loading current i₂ being calculated by current flowing throughtransistor Min2:

i ₂=½k ₂(V _(in2) −V _(S2) −V _(t2))²

Loading current i₂ being calculated by current flowing throughtransistor Mb2:

i ₂ =k ₄(V _(in1) −V _(S) −V _(t4))(V _(S2) −V _(S))

where

${{i_{1} + i_{2}} = I};{k_{1} = {k_{2} = {\mu_{n}{C_{ox}\left( \frac{W}{L} \right)}_{1}}}};{k_{3} = {k_{4} = {\mu_{n}{C_{ox}\left( \frac{W}{L} \right)}_{3}}}};$

V_(S) is the source voltage of transistor Mb1 and Mb2; V_(S1) and V_(S2)are the source voltages of transistors Min1 and Min2 respectively.

When the input voltage difference ΔV_(in) is small, transistors Mb1 andMb2 operate in the triode region, and the source voltages of these fourtransistors Min1, Min2, Mb1, Mb2 are close. In addition, the thresholdvoltages of these four transistors Min1, Min2, Mb1, Mb2 are also close.In addition, V_(t1)=V_(t2)=V_(t3)=V_(t4)=V_(t) may be substituted in theabove formulas. After formula manipulation and simplification, theloading currents i₁, i₂ may be expressed as:

$\begin{matrix}{i_{1} \cong {\frac{1}{2} + {{\sqrt{\mu_{n}{C_{ox}\left( {W/L} \right)}_{1}I}\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}\left( \frac{\Delta \; v_{i\; n}}{2} \right) \times \sqrt{1 - {{\frac{\mu_{n}{C_{ox}\left( {W/L} \right)}_{1}}{I}\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}^{2}\left( \frac{\Delta \; v_{i\; n}}{2} \right)^{2}}}}}} & \left( {{{Eq}.\mspace{14mu} 10}A} \right) \\{i_{2} \cong {\frac{1}{2} - {{\sqrt{\mu_{n}{C_{ox}\left( {W/L} \right)}_{1}I}\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}\left( \frac{\Delta \; v_{i\; n}}{2} \right) \times \sqrt{1 - {{\frac{\mu_{n}{C_{ox}\left( {W/L} \right)}_{1}}{I}\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}^{2}\left( \frac{\Delta \; v_{i\; n}}{2} \right)^{2}}}}}} & \left( {{{Eq}.\mspace{14mu} 10}B} \right)\end{matrix}$

Based on Eq. 10A and Eq. 10B, when

$\begin{matrix}{{\frac{\Delta \; v_{i\; n}}{2}\frac{\sqrt{{I/\mu_{n}}{C_{ox}\left( {W/L} \right)}_{1}}}{1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}}},} & \left( {{Eq}.\mspace{14mu} 11} \right)\end{matrix}$

the loading currents i₁ and i₂ may be approximately represented as alinear relation as follows:

$\begin{matrix}{i_{1} \cong {\frac{1}{2} + {{\sqrt{\mu_{n}{C_{ox}\left( {W/L} \right)}_{1}I}\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}\left( \frac{\Delta \; v_{i\; n}}{2} \right)}}} & \left( {{{Eq}.\mspace{14mu} 12}A} \right) \\{i_{2} \cong {\frac{1}{2} - {{\sqrt{\mu_{n}{C_{ox}\left( {W/L} \right)}_{1}I}\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}\left( \frac{\Delta \; v_{i\; n}}{2} \right)}}} & \left( {{{Eq}.\mspace{14mu} 12}B} \right)\end{matrix}$

That is, when the condition in Eq. 11 is satisfied, the relation betweenthe loading current i₁ and the input voltage difference ΔV_(in) islinear. The transconductance Gm of the input stage circuit 301 shown inFIG. 4A is:

$\begin{matrix}{G_{m} = {\frac{i_{1}}{\Delta \; {v_{i\; n}/2}} = {\sqrt{\mu_{n}{C_{ox}\left( {W/L} \right)}_{1}I}\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}}} & \left( {{Eq}.\mspace{14mu} 13} \right)\end{matrix}$

Comparing Eq. 13 with Eq. 4, the transconductance Gm of the differentialpair (four transistor architecture, 4T) as shown in FIG. 4A is

$\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack$

times of the transconductance Gm of the differential pair (twotransistor architecture, 2T) as shown in FIG. 2A (the transconductanceGm is reduced). However, comparing Eq. 11 with Eq. 2, the linear rangeof the 4T differential pair is

$\frac{1}{\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}$

times of the linear range of the 2T differential pair. In other words,the proposed differential input stage circuit shown in FIG. 4A is ableto extend the linear range for the input voltage difference ΔV_(in). Inaddition, a desired linear range can be designed by appropriatelyadjusting the size of the four transistors Mb1, Mb2, Min1, Min2(adjusting

$\left. {\left( \frac{W}{L} \right)_{1}\mspace{14mu} {and}\mspace{14mu} \left( \frac{W}{L} \right)_{3}} \right)$

based on the formula

$\frac{1}{\left\lbrack {1 - \frac{3\left( {W/L} \right)_{1}}{2\left\lbrack {\left( {W/L} \right)_{1} + \left( {W/L} \right)_{3}} \right\rbrack}} \right\rbrack}.$

FIG. 4B shows a diagram illustrating a transconductance of thedifferential input stage circuit shown in FIG. 4A. The horizontal axisis the input voltage difference ΔV_(in). When the input voltagedifference ΔV_(in) exceeds +ΔV2 (or less than −ΔV2), thetransconductance Gm becomes 0, and hence the differential pair does notworker properly under such input voltage condition. Compare FIG. 4B withFIG. 2B, the input voltage range that results in a stabletransconductance Gm is enlarged in FIG. 4B. ΔV2>ΔV1, and hence thelinear range of the differential pair is greatly enhanced.

In the above embodiment NMOS transistors are used in the differentialinput stage circuit 301. In another embodiment, the differential inputstage circuit 351 may include PMOS transistors instead. FIG. 5 shows anoperational amplifier circuit having a bias control circuit and a PMOSdifferential pair according to an embodiment of the invention. Thecurrent source I_(P) is coupled to a supply voltage Vdd. The connectiontopology and the operation are similar to those in FIG. 4A and thus arenot repeated herein. In this embodiment, transistors Min1, Min2, Mb1,Mb2 are PMOS transistors. The first terminal, the second terminal, andthe control terminal of a PMOS transistor may correspond to the drainterminal, the source terminal, and the gate terminal, respectively.

FIG. 6 shows a rail-to-rail operational amplifier circuit having biascontrol circuits according to an embodiment of the invention. Inaddition to transistors Min1 a, Min2 a, Mb1 a, Mb2 a in whichinterconnections are similar to the ones shown in FIG. 4A, thedifferential input stage circuit 401 b in FIG. 6 also includes a firstcomplementary current source I_(P) and complementary transistors Min1 b,Min2 b, Mb1 b and Mb2 b. The complementary transistor Min1 b has a firstterminal, a second terminal, and a control terminal for receiving thefirst input signal V_(in1). The complementary transistor Min2 b has afirst terminal, a second terminal, and a control terminal for receivingthe second input signal V_(in2). The complementary transistor Mb1 b hasa first terminal coupled to the second terminal of the complementarytransistor Min1 b, a second terminal coupled to the first complementarycurrent source I_(P), and a control terminal coupled to the controlterminal of the complementary transistor Min2 b. The complementarytransistor Mb2 b has a first terminal coupled to the second terminal ofthe complementary transistor Min2 b, a second terminal coupled to thefirst complementary current source I_(P), and a control terminal coupledto the control terminal of the complementary transistor Min1 b. Theloading stage circuit 402 is coupled to the first terminal of thecomplementary transistor Min1 b and the first terminal of thecomplementary transistor Min2 b.

The gate terminal of transistor Min1 a and the gate terminal of thecomplementary transistor Min1 b are coupled together. The gate terminalof transistor Min2 a and the gate terminal of the complementarytransistor Min2 b are also coupled together. The connection relationbetween complementary transistors Min1 b, Min2 b, Mb1 b, Mb2 b issimilar to that shown in FIG. 5. The rail-to-rail operational amplifiercircuit 4 is able to provide a wider dynamic range for input signals andoutput signals.

In one embodiment, the sizes of the complementary transistors MP1 andMP2 are substantially equal. The sizes of the complementary transistorsMP3 and MP4 are substantially equal.

FIG. 7 shows an example implementation of the loading stage circuit andthe output stage circuit together with the rail-to-rail architectureshown in FIG. 6. The loading stage circuit 102 in this example includesthe NMOS transistors Mln1, Mln2 and PMOS transistors MPlp1, Mlp26. Theoutput stage circuit 103 in this example includes the NMOS transistorMon and PMOS transistor Mop. FIG. 7 shows merely an exemplaryimplementation. The circuit architecture for different applications maybe modified correspondingly based on the design constraints, such as thevoltage gain and bandwidth requirements.

According to another embodiment of the present disclosure, a voltagemaintaining circuit is provided for tracking an input common modevoltage Vcm of the differential input pair so that the differential pairoperates at the boundary of the triode region and the saturation region.The input common mode voltage Vcm of the differential input pair isequivalent to an average of the first input signal V_(in1) and thesecond input signal Vin2.

FIG. 8A shows an operational amplifier circuit having a voltagemaintaining circuit and an NMOS differential pair according to anembodiment of the invention. The control terminal of the first inputtransistor Min1 receives a first input signal V_(in1). The controlterminal of the second input transistor Min2 receives a second inputsignal V_(in2). The first and the second input signals V_(in1), V_(in2)jointly form a pair of the differential input signals V_(in1), V_(in2).

The first branch circuit includes transistors Mt11 (first trackingtransistor) and Mt12 (second tracking transistor), and the second branchcircuit includes transistors Mt21 (third tracking transistor) and Mt22(fourth tracking transistor).

The first terminals of transistors Mt11, Mt12, Mt21 and Mt22 are coupledto the loading stage circuit. The control terminals of transistors Mt11and Mt21 are coupled to the control terminal of the first inputtransistor Min1. The control terminals of Mt12 and Mt22 are coupled tothe control terminal of the second input transistor Min2. The secondterminals of transistor Mt11 and Mt21 are coupled to the first terminalof the first input transistor Min1. The second terminals of transistorMt21 and transistor Mt22 are coupled to the first terminal of the secondinput transistor Min2.

The loading stage circuit 302 is coupled to the first terminals of theinput transistor Min1 and the second input transistor Min2, forgenerating an output signal V_(O) at an output terminal of theoperational amplifier circuit 11 b.

In the example shown in FIG. 8A, transistors Min1, Min2, Mb1 and Mb2 areNMOS transistors. The first terminal, the second terminal, and thecontrol terminal of an NMOS transistor may correspond to the drainterminal, the source terminal, and the gate terminal, respectively.

In one embodiment, the sizes (gate width W and gate length L) of theinput transistors Min1 and Min2 are substantially equal (represented as

$\left( \frac{W}{L} \right)_{1}\mspace{11mu}$

in the following formulas). The sizes of transistors Mt11 and Mt12 aresubstantially equal (represented as

$\left( \frac{W}{L} \right)_{3}\mspace{11mu}$

in the following formulas). The sizes of transistors Mt21 and Mt22 aresubstantially equal (represented as

$\left( \frac{W}{L} \right)_{5}\mspace{11mu}$

in the following formulas).

Refer to FIG. 8A, when the input voltage difference ΔV_(in)(ΔV_(in)=V_(in1)−V_(in2)) is small, voltages of the second terminal oftransistors Mt11 and Mt12 basically remain constant due to thecharacteristic of the differential pair. That is, a virtual groundphenomenon exists at the first terminals of the first input transistorMin1 and the second input transistor Min2. Due to the virtual groundphenomenon, voltages of the first terminals of the first and the secondinput transistors, that is, Vd1 and Vd2, can be remained constantly. Thevoltage of the first terminal Vd1 of the first input transistor Min1 canbe obtained by subtracting the gate-to-source voltage Vgs of the firstinput transistor Mt11 from an input common mode voltage Vcm. Similarly,the voltage of the first terminal Vd2 of the second input transistorMin2 can be obtained by subtracting the gate-to-source voltage Vgs ofthe second input transistor Mt22 from the input common mode voltage Vcm.

Based on the constant voltages at their first terminals, both the firstinput transistor Min1 and the second input transistor Min2 arecontrolled to operate at the boundary of the triode region and thesaturation region. Because both the first input transistor Min1 and thesecond input transistor Min2 operate in the triode region and thesaturation region, the linearity of the differential input pair isbetter. Therefore, the design of the voltage maintaining circuit canimprove linearity of the differential pair.

By assuming threshold voltages of all transistors in FIG. 8A areequivalent, the current and voltage of the circuit shown in FIG. 8A isprovided below.

Firstly, the first input transistor Min1 operates in the triode region,and the loading current i1 can be calculated by the current flowingthrough the first input transistor Min1 as represented below, in which

$k_{1} = {\mu_{n}{C_{ox}\left( \frac{W}{L} \right)}_{1}}$

Loading current i₁ being calculated by current flowing throughtransistor Min1:

i ₁ =k ₁(V _(in1) −V _(S) −V _(t))(V _(D1) −V _(S))

For the first branch circuit, the first branch current Ib1 is equivalentto summation of the first part of loading current i_(d11) as the currentflowing through transistor Mt11 and the second part of loading currenti_(d12) as the current flowing through transistor Mt12, that is,i_(b1)=i_(d11)+i_(d12). Transistors Mt11 and Mt12 operate in thesaturation region, and the currents flowing through transistors Mt11 andMt12 are shown below, together with the first branch current Ib1. In thefollowing formulas,

${{k_{3} = {\mu_{n}{C_{ox}\left( \frac{W}{L} \right)}_{3}}},{{{and}\mspace{14mu} k_{5}} = {\mu_{n}{{C_{ox}\left( \frac{W}{L} \right)}_{5}.}}}}\mspace{11mu}$

First part of loading current i_(d11) being calculated by currentflowing through transistor Mt11; i_(d11)=½k₃(V_(in1)−V_(D1)−V_(t))²Second part of loading current i_(d12) being calculated by currentflowing through transistor Mt12; i_(d12)=½k₅(V_(in2)−V_(D1)−V_(t))²Loading current i_(b1) being calculated by current flowing through thefirst branch circuit:i_(b1)=i_(d11)+i_(d12)=½k₃(V_(in1)−V_(D1)−V_(t))²+½k₅(V_(in2)−V_(D1)−V_(t))²

Similarly, the second input transistor Min2 operates in the trioderegion, and the drain current of the second input transistor Min2 can berepresented below, in which

$k_{2} = {\mu_{n}{C_{ox}\left( \frac{W}{L} \right)}_{1}}$

Loading current being calculated by current flowing through transistorMin2:

i ₂ =k ₂(V _(in2) −V _(S) −V _(t))(V _(D2) −V _(S))

For the second branch circuit, the second branch current i_(b2) isequivalent to summation of the first part of loading current i_(d21) asthe current flowing through transistor Mt21 and the second part ofloading current i_(d22) as the current flowing through transistor Mt22,that is, i_(b2)=i_(d21)+i_(d22). The currents flowing throughtransistors Mt11 and Mt12 are shown below, together with the firstbranch current i_(b1). In the following formulas,

${k_{4} = {\mu_{n}{C_{ox}\left( \frac{W}{L} \right)}_{3}}},{{{and}\mspace{14mu} k_{5}} = {\mu_{n}{{C_{ox}\left( \frac{W}{L} \right)}_{5}.}}}$

First part of loading current i_(d21) being calculated by currentflowing through transistor Mt11: i_(d21)=½k₄(V_(in2)−V_(D2)−V_(t))²Second part of loading current i_(d22) being calculated by currentflowing through transistor Mt12: i_(d22)=½k₆(V_(in1)−V_(D2)−V_(t))²Loading current i_(b2) being calculated by current flowing through thesecond branch circuit:i_(b2)=i_(d21)+i_(d22)=½k₄(V_(in2)−V_(D2)−V_(t))²+½k₆(V_(in1)−V_(D2)−V_(t))²

In one embodiment, the sizes of transistors Min1 a and Min2 a aresubstantially equal. The sizes of transistors Mt11 a, Mt12 a, Mt21 a andMt22 a are substantially equal.

$\begin{matrix}{i_{1} = {\frac{1}{2} + {\frac{K}{2}\sqrt{k_{1}I}\left( \frac{\Delta \; V_{in}}{2} \right)\sqrt{1 - \frac{\left( \frac{\Delta \; v_{in}}{2} \right)^{2}}{\frac{4l}{K^{2}k_{1}}}}}}} & \left( {{{Eq}.\mspace{14mu} 14}A} \right) \\{i_{2} = {\frac{1}{2} - {\frac{K}{2}\sqrt{k_{1}I}\left( \frac{\Delta \; V_{in}}{2} \right)\sqrt{1 - \frac{\left( \frac{\Delta \; v_{in}}{2} \right)^{2}}{\frac{4I}{K^{2}k_{1}}}}}}} & \left( {{{Eq}.\mspace{14mu} 14}B} \right)\end{matrix}$

In Eq. 14A and Eq. 14B, K is less than 1 and can be represented by k1,k2, k3, k4, and k5, as shown by Eq. 15.

$\begin{matrix}{K = \frac{k_{1}^{2} + {2k_{3}^{2}} + {3k_{1}k_{3}} - {3k_{1}k_{5}}}{k_{1}^{2} + k_{3}^{2} + k_{5}^{2} + {2k_{1}k_{3}} + {2k_{1}k_{5}} + {2k_{3}k_{5}}}} & \left( {{Eq}.\mspace{14mu} 15} \right)\end{matrix}$

Based on Eq. 14A and Eq. 14B, when

$\begin{matrix}{{{\frac{\Delta \; v_{in}}{2}{\frac{2}{K}\sqrt{\frac{1}{k\; 1}}}} = {\frac{2}{K}\sqrt{\frac{I}{\mu_{n}{C_{ox}\left( \frac{W}{L} \right)}_{1}}}}},} & \left( {{Eq}.\mspace{14mu} 16} \right)\end{matrix}$

the drain currents i1 and i2 may be approximately represented as alinear relation as follows:

$\begin{matrix}{i_{1} \cong {\frac{1}{2} + {\frac{K}{2}\sqrt{k_{1}I}\left( \frac{\Delta \; V_{in}}{2} \right)}}} & \left( {{{Eq}.\mspace{14mu} 17}A} \right) \\{i_{2} \cong {\frac{1}{2} - {\frac{K}{2}\sqrt{k_{1}I}\left( \frac{\Delta \; V_{in}}{2} \right)}}} & \left( {{{Eq}.\mspace{14mu} 17}B} \right)\end{matrix}$

The is, when the condition in Eq. 16 is satisfied, the relation betweenthe drain currents and the input voltage difference ΔV_(in) is linear.The transconductance (Gm) of the differential input pair shown in FIG.8A is:

$\begin{matrix}{G_{m} = {\frac{i_{1}}{\Delta \; {v_{in}/2}} = {{\frac{K}{2}\sqrt{k_{1}I}} = {\frac{K}{2}\sqrt{\mu_{n}{C_{OX}\left( {W/L} \right)}_{1}I}}}}} & \left( {{Eq}.\mspace{14mu} 18} \right)\end{matrix}$

Comparing Eq. 17 with Eq. 4, the transconductance Gm of the differentialpair (six transistor architecture, 6T) as shown in FIG. 8A is K/2 timesof the transconductance Gm of the differential pair (two transistorarchitecture, 2T) as shown in FIG. 2A (the transconductance Gm in FIG.8A is reduced to less than half of the transconductance Gm in FIG. 2A).As defined in Eq. 15, K is always smaller than “1”. Based on the schemeshown in FIG. 8A, range of the input voltage difference ΔV_(in) can beincreased to 2/K times under the circumstance that the differentialinput pair having same linearity. As K is smaller than 1, the multiple2/K is greater than 2, which implies that range of the input voltagedifference ΔV_(in) is increased by at least two times. In addition, adesired linear range can be designed by appropriately adjusting aspectratios of transistors Min1, Min2, Mt11, Mt12, Mt21, Mt22.

FIG. 8B shows a diagram illustrating the loading currents versus inputvoltage difference of the differential input stage circuit shown in FIG.8A. The horizontal axis is the input voltage difference ΔV_(in). Whenthe input voltage difference ΔV_(in) exceeds +ΔV2 (or less than −ΔV2),the loading currents i₁, i₂ become constant, and hence the differentialpair does not worker properly under such input voltage condition.Compare FIG. 8C with FIG. 2C, the input voltage range that results in arelation corresponding to a constant slope is enlarged in FIG. 8C.ΔV2>ΔV1, and hence the linear range of the differential pair is greatlyenhanced.

In the above embodiment NMOS transistors are used in the differentialinput stage circuit 301. In another embodiment, the differential inputstage circuit 351 may include PMOS transistors instead.

FIG. 9 shows an operational amplifier circuit having a voltagemaintaining circuit and a PMOS differential pair according to anembodiment of the invention. The connection topology and the operationare similar to those in FIG. 8A and thus are not repeated herein. Inthis embodiment, transistors Min1, Min2, Mt11, Mt12, Mt21 and Mt22 arePMOS transistors. The first terminal, the second terminal, and thecontrol terminal of a PMOS transistor may correspond to the drainterminal.

In one embodiment, the sizes of the input transistors Min1 a and Min2 aare substantially equal. The sizes of transistors Mt1111 a, Mt12 a, Mt21a and Mt22 a are substantially equal.

FIG. 10 shows a rail-to-rail operational amplifier circuit havingvoltage maintaining circuits according to an embodiment of theinvention. The rail-to-rail operational amplifier circuit 60 is able toprovide a wider dynamic range for input signals and output signals. Asshown in FIG. 10, the differential input stage includes two complementportions, that is, a first portion and a second portion. In FIG. 10, thefirst portion and the second portion are assumed to be the lower partand the upper part of the differential input stage circuit,respectively.

In FIG. 10, the first portion of the differential input stage is similarto the circuit shown in FIG. 8A and includes a first input circuit, afirst voltage maintaining circuit, and a current source. The first inputcircuit includes the input transistors Min1 a and Min2 a, the firstvoltage maintaining circuit includes transistors Mt1111 a, Mt12 a, Mt21a and Mt22 a.

In FIG. 10, the second portion of the differential input stage issimilar to the circuit shown in FIG. 9 and includes a second inputcircuit, a second voltage maintaining circuit, and a second currentsource. The second input circuit includes the input transistors Min1 band Min2 b, and the second voltage maintaining circuit includestransistors Mt11 b, Mt12 b, Mt21 b and Mt22 b.

FIG. 11 shows an example implementation of the loading stage circuit andthe output stage circuit together with the rail-to-rail architectureshown in FIG. 10. The loading stage circuit 102 in this example includesthe NMOS transistors Mln1, Mln2 and PMOS transistors MPlp1, Mlp26. Theoutput stage circuit 103 in this example includes the NMOS transistorMon and PMOS transistor Mop. FIG. 11 shows merely an exemplaryimplementation. The circuit architecture for different applications maybe modified correspondingly based on the design constraints, such as thevoltage gain and bandwidth requirements.

In order to reduce the amount of transistors in the voltage maintainingcircuit, the circuit shown in FIG. 8A and be modified to obtain FIG. 12.FIG. 12 shows an operational amplifier circuit having a voltagemaintaining circuit and an NMOS differential pair according to anotherembodiment of the invention.

The first branch circuit includes a transistor Mt1 (as a first trackingtransistor) and the second branch circuit includes a transistor Mt2 (asa second tracking transistor). The first terminals of transistors Mt1and Mt2 are coupled to the loading stage circuit 702. The controlterminal of transistor Mt1 is coupled to the control terminal of thefirst input transistor Min1. The control terminal of transistor Mt2 iscoupled to the control terminal of the second input transistor Min2. Thesecond terminal of transistor Mt1 is coupled to the first terminal ofthe first input transistor Min1. The second terminal of transistor Mt2is coupled to the first terminal of the second input transistor Min2.

In FIG. 12, the voltage of the first terminal of first input transistor(Min1) Vd1 can be obtained by subtracting the gate-to-source voltage Vgsof the first input transistor Mt1 from the first input signal Vin1, andthe voltage of the first terminal of the second input transistor (Min2)Vd2 can be obtained by subtracting the gate-to-source voltage Vgs of thesecond input transistor Mt2 from the second input signal Vin2.

When the input voltage changes, difference between the first inputsignal V_(in1) and the drain terminal of the first input transistor Min1is the gate-to-source voltage Vgs of transistor Mt1, which implies thatthe first input transistor Min1 operates at the boundary of the trioderegion and the saturation region. Similarly, difference between thesecond input signal V_(in2) and the drain terminal of the second inputtransistor Min2 is the gate-to-source voltage Vgs of transistor Mt2, andthe second input transistor Min2 operates at the boundary of the trioderegion and the saturation region as well. Because both the first inputtransistor Min1 and the second input transistor Min2 operate at he thetriode region and the saturation region, the linearity of FIG. 12A isbetter, compared with the ones in FIG. 2A.

FIG. 13 shows an operational amplifier circuit having a voltagemaintaining circuit and a PMOS differential pair according to anotherembodiment of the invention. The connection topology and the operationare similar to those in FIG. 12 and thus are not repeated herein. Inthis embodiment, transistors Min1, Min2, Mt11, Mt1 and Mt2 are PMOStransistors. The first terminal, the second terminal, and the controlterminal of a PMOS transistor may correspond to the drain terminal, thesource terminal, and the gate terminal, respectively.

FIG. 14 shows a rail-to-rail operational amplifier circuit havingvoltage maintaining circuits according to another embodiment of theinvention. The rail-to-rail operational amplifier circuit 80 is able toprovide a wider dynamic range for input signals and output signals. Asshown in FIG. 14, the differential input stage includes two complementportions, that is, a first portion and a second portion. In FIG. 14, thefirst portion and the second portion are assumed to be the lower partand the upper part of the differential input stage circuit,respectively.

In FIG. 14, the first portion of the differential input stage circuit issimilar to the circuit shown in FIG. 12 and includes a first inputcircuit, a first voltage maintaining circuit, and a current source. Thefirst input circuit includes the input transistors Min1 a and Min2 a,the first voltage maintaining circuit includes transistors Mt1 a, Mt2 a.

In FIG. 14, the second portion of the differential input stage issimilar to the circuit shown in FIG. 13 and includes a second inputcircuit, a second voltage maintaining circuit, and a second currentsource. The second input circuit includes the input transistors Min1 band Min2 b, and the second voltage maintaining circuit includestransistors Mt1 b, Mt2 b.

FIG. 15 shows an example implementation of the loading stage circuit andthe output stage circuit together with the rail-to-rail architectureshown in FIG. 14. The loading stage circuit 802 in this example includesthe NMOS transistors Mln1, Mln2 and PMOS transistors MPlp1, Mlp26. Theoutput stage circuit 103 in this example includes the NMOS transistorMon and PMOS transistor Mop. FIG. 15 shows merely an exemplaryimplementation. The circuit architecture for different applications maybe modified correspondingly based on the design constraints, such as thevoltage gain and bandwidth requirements.

In LCD driver applications, an operational amplifier circuit may includemultiple differential pairs to achieve voltage interpolation function.Such circuit design can reduce chip area and production cost. In someapplications, more differential pairs may be accommodated. The loadingstage circuit is not illustrated in following figures for simplicityreason.

FIG. 16 shows an operational amplifier circuit including multipledifferential pairs according to one embodiment of the invention. In thisexample, the differential input stage circuit 90 includes fourdifferential pairs 931-934. Note that the number of total differentialpairs may be other numbers, four differential pairs illustrated in thisexample is just exemplary rather than limiting. The first differentialpair 931 receives an input signal V_(G1) and the output signal V_(O) fedback from the loading stage circuit 102. Similarly, the seconddifferential pair 932 receives another input signal V_(G2) and theoutput signal V_(O). The output signal V_(O) is an interpolation resultof the input signals V_(G1)-V_(G4). By adopting the above mentioned 4Tand/or 6T architecture in the differential pairs 931-934, the extendedlinear range helps to reduce the output error of the operationalamplifier circuit 9.

According to the embodiments given above, the operational amplifiercircuit can effectively extend the linear range for the input voltagedifference ΔV_(in). The extended linear range can be designed to adesired value by appropriately adjusting the transistor size. Inaddition, the operational amplifier circuit can include multiple 4Tand/or 6T differential pairs to achieve voltage interpolation function.

To further illustrate the concept that how differential pairs in thedifferential input stage circuit are placed in parallel, twodifferential pairs are illustrated in the examples shown in FIG. 17A,18A and FIG. 19A.

FIG. 17A is corresponding the case regarding the differential inputstage circuit uses the bias control circuit. FIGS. 18A and 19A arecorresponding to the cases regarding the differential input stagecircuit uses the first type and the second type of the voltagemaintaining circuit, respectively.

FIG. 17A shows a differential input stage circuit with voltageinterpolation function according to one embodiment of the invention. Thedifferential input stage circuit 901 a includes a first differentialpair 931 a and a second differential pair 932 a. The differential inputstage circuit 901 a is utilized for interpolating input signals V_(G1)and V_(G2) to generate the output signal V_(Out) according to asuperposition principle. The output signal V_(Out) of the differentialoperational amplifier is fed back to the differential input stagecircuit 901 a in this example.

The transconductance of the first differential pair 931 a is Gm1, andthe transconductance of the second differential pair 932 a is Gm2. Bythe superposition principle, the output signal V_(Out) may be expressedas:

$\begin{matrix}{V_{Out} = \frac{{{Gm}\; 1 \times V_{G\; 1}} + {{Gm}\; 2 \times V_{G\; 2}}}{{{Gm}\; 1} + {{Gm}\; 2}}} & \left( {{Eq}.\mspace{14mu} 19} \right)\end{matrix}$

Gm1=Gm2 in an ideal case (V_(O)=0.5×V_(G1)+0.5×V_(G2)). However, referto FIGS. 2A and 2B, the linear range of the 2T differential pair isrelatively small. Consequently, Gm1≠Gm2 when the voltage differencebetween the input signals V_(G1) and V_(G2) is large. Therefore the realoutput signal V_(Out) deviates from the ideal value. FIG. 17B shows thevoltage levels of signals shown in FIG. 17A. There is an error ΔV3between the ideal output and the real output signal.

FIG. 18A shows a differential input stage circuit with voltageinterpolation function according to one embodiment of the invention. Thedifferential input stage circuit 901 b includes two subsets, a firstsubset including a current source I_(S1) and transistors Min11, Min12,Mb11, Mb12, and a second subset including a current source I_(S2) andtransistors Min21, Min22, Mb21, Mb22. All components andinterconnections in both the first and the second subsets are connectedas the ones shown in FIG. 4A.

In FIG. 18A, the control terminal of transistor Min21 receives the inputsignal V_(G2), and the control terminal of transistor Min22 receives theoutput signal V_(Out). In FIG. 18A, the control terminals of the inputtransistors Min12 and Min22 are assumed to be coupled together toaccomplish the voltage interpolation function. Accordingly, the outputsignal V_(Out) is an interpolation result of the input signals V_(G1)and V_(G2). The interpolation formula has been shown in the example ofFIG. 17A.

In one embodiment, transistors Min21, Min22, Mb21, Mb22 are NMOStransistors, which are of the same type as transistors Min11, Min12,Mb11, Mb12. In one embodiment, the sizes of transistors Min21 and Min22are substantially equal. The size of transistors Mb21 and Mb22 aresubstantially equal.

Because 6T differential pairs are used in the example in FIG. 18A, thelinear range for input voltage difference ΔV_(in) is extended. As aresult, the difference between the transconductance Gm1 of the firstdifferential pair 931 b and the transconductance Gm2 of the seconddifferential pair 932 b becomes smaller. The real output signalV_(Out(Real)) will be closer to the ideal output signal V_(Out(Ideal)).

FIG. 18B shows the voltage levels of signals shown in FIG. 18A. There isan error ΔV4 between the ideal output and the real output signal. Ascompared to FIG. 17B, ΔV4<ΔV3. The extended linear range for thedifferential pair improves the accuracy of the voltage interpolationresult.

FIG. 19A shows a differential input stage circuit with voltageinterpolation function according to another embodiment of the invention.The differential input stage circuit 901 c includes two subsets, a firstsubset including a current source I_(S1) and transistors Min11, Min12,Mt11 a, Mt11 b, Mt12 a, Mt12 b, and a second subset including a currentsource I_(S2) and transistors Min21, Min22, Mt21 a, Mt21 b, Mt22 a, Mt22b. All components and interconnections in both the first and the secondsubsets are connected as the ones shown in FIG. 8A.

In FIG. 19A, the control terminals of transistors Min21 and Mt21 areceives the input signal V_(G2), and the control terminals oftransistors Min22, Mt22 b receives the output signal V_(Out). In FIG.19A, the control terminals of the input transistors Min12 and Min22 areassumed to be coupled together to accomplish the voltage interpolationfunction. Accordingly, the output signal V_(Out) is an interpolationresult of the input signals V_(G1) and V_(G2). The interpolation formulahas been shown in the example of FIG. 17A.

In one embodiment, transistors Min21, Min22, Mt21 a, Mt21 b, Mt22 a,Mt22 b are NMOS transistors, which are of the same type as transistorsMin11, Min12, Mt11 a, Mt11 b, Mt12 a, Mt12 b. In one embodiment, thesizes of transistor Min21 and Min22 are substantially equal. The sizesof transistors Mt21 a, Mt21 b, Mt22 a and Mt22 b are substantiallyequal.

Because 6T differential pairs are used in the example in FIG. 19A, thelinear range for input voltage difference ΔV_(in) is extended. As aresult, the difference between the transconductance Gm1 of the firstdifferential pair 931 c and the transconductance Gm2 of the seconddifferential pair 932 c becomes smaller. The real output signal will becloser to the ideal output signal.

FIG. 19B shows the voltage levels of signals shown in FIG. 19A. There isan error ΔV5 between the ideal output and the real output signal. Ascompared to FIG. 17B, ΔV5<ΔV3. The extended linear range for thedifferential pair improves the accuracy of the voltage interpolationresult.

In LCD driver applications, the operational amplifier circuit is oftenpreceded by a digital-to-analog converter (DAC). The proposedoperational amplifier circuit adopts different structures to allow alarger range for the input voltage difference. Therefore the resolutionrequirement for the preceding DAC can be relaxed. In other words, thehardware cost for the DAC circuit can be effectively reduced because ofthe extended linear range of the proposed operational amplifier circuit.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the disclosed embodiments.It is intended that the specification and examples be considered asexemplary only, with a true scope of the disclosure being indicated bythe following claims and their equivalents.

What is claimed is:
 1. An operational amplifier circuit, comprising: a differential input stage circuit, comprising: a first input circuit, comprising: a first input transistor, having a first terminal, a second terminal, and a control terminal for receiving a first input signal; and a second input transistor, having a first terminal, a second terminal, and a control terminal for receiving a second input signal; a first voltage maintaining circuit, comprising: a first branch circuit, coupled to the first terminal and the control terminal of the first input transistor, wherein the first branch circuit receives the first input signal; and a second branch circuit, coupled to the first terminal and the control terminal of the second input transistor, wherein the second branch circuit receives the second input signal; and a first current source, coupled to the second terminals of the first input transistor and the second input transistor; and a loading stage circuit, coupled to the first voltage maintaining circuit, for generating a first stage output.
 2. The operational amplifier circuit according to claim 1, wherein the differential input stage circuit further comprises: a second input circuit, comprising: a third input transistor, having a first terminal, a second terminal, and a control terminal for receiving a third input signal; and a fourth input transistor, having a first terminal, a second terminal, and a control terminal for receiving a fourth input signal; and a second voltage maintaining circuit, comprising a third branch circuit, coupled to the first terminal and the control terminal of the third input transistor, wherein the third branch circuit receives the third input signal; and a fourth branch circuit, coupled to the first terminal and the control terminal of the fourth input transistor, wherein the fourth branch circuit receives the fourth input signal; and a second current source, coupled to the second terminals of the third input transistor and the fourth input transistor, wherein the loading stage circuit is coupled to the second voltage maintaining circuit.
 3. The operational amplifier circuit according to claim 2, wherein the first input signal and the third input signal are identical, and the second input signal and the fourth input signal are identical.
 4. The operational amplifier circuit according to claim 3, wherein the first input transistor and the third input transistor are complement; the second input transistor and the fourth input transistor are complement; and the first voltage maintaining circuit and the second voltage maintaining circuit are complement.
 5. The operational amplifier circuit according to claim 1, wherein the first branch circuit comprises a first tracking transistor and a second tracking transistor, and the second branch circuit comprises a third tracking transistor and a fourth tracking transistor, wherein each of the first tracking transistor, the second tracking transistor, the third tracking transistor and the fourth tracking transistor comprises a first terminal, a second terminal, and a control terminal.
 6. The operational amplifier circuit according to claim 5, wherein the first terminals of the first tracking transistor, the second tracking transistor, the third tracking transistor and the fourth tracking transistor are coupled to the loading stage circuit; the control terminals of the first tracking transistor and the third tracking transistor are coupled to the control terminal of the first input transistor for receiving the first input signal; the control terminals of the second tracking transistor and the fourth tracking transistor are coupled to the control terminal of the second input transistor for receiving the second input signal; the second terminals of the first tracking transistor and the second tracking transistor are coupled to the first terminal of the first input transistor; and the second terminals of the third tracking transistor and the fourth tracking transistor are coupled to the first terminal of the second input transistor.
 7. The operational amplifier circuit according to claim 5, wherein a size of the first input transistor is substantially equal to a size of the second input transistor, a size of the first tracking transistor is substantially equal to a size of the second tracking transistor, and a size of the third tracking transistor is substantially equal to a size of the fourth tracking transistor.
 8. The operational amplifier circuit according to claim 5, wherein the first input transistor, the second input transistor, the first tracking transistor, the second tracking transistor, the third tracking transistor, and the fourth tracking transistor are NMOS transistors; or the first input transistor, the second input transistor, the first tracking transistor, the second tracking transistor, the third tracking transistor, and the fourth tracking transistor are PMOS transistors.
 9. The operational amplifier circuit according to claim 1, wherein the first branch circuit comprises a first tracking transistor and the second branch circuit comprises a second tracking transistor, wherein each of the first tracking transistor and the second tracking transistor comprises a first terminal, a second terminal, and a control terminal.
 10. The operational amplifier circuit according to claim 9, wherein the first terminals of the first tracking transistor and the second tracking transistor are coupled to the loading stage circuit; the control terminal of the first tracking transistor is coupled to the control terminal of the first input transistor for receiving the first input signal; the control terminal of the second tracking transistor is coupled to the control terminal of the second input transistor for receiving the second input signal; the second terminal of the first tracking transistor is coupled to the first terminal of the first input transistor; and the second terminal of the second tracking transistor is coupled to the first terminal of the second input transistor.
 11. The operational amplifier circuit according to claim 9, wherein a size of the first input transistor is substantially equal to a size of the second input transistor, and a size of the first tracking transistor is substantially equal to a size of the second tracking transistor.
 12. The operational amplifier circuit according to claim 9, wherein the first input transistor, the second input transistor, the first tracking transistor, and the second tracking transistor are NMOS transistors; or the first input transistor, the second input transistor, the first tracking transistor, and the second tracking transistor are PMOS transistors.
 13. The operational amplifier circuit according to claim 1, further comprising: an output stage circuit, coupled to the loading stage circuit, for receiving the first stage output and generating a second stage output.
 14. The operational amplifier circuit according to claim 1, wherein a first loading current flows from the loading stage circuit to the first input circuit through the first branch circuit, and a second loading current flows from the loading stage circuit to the first input circuit through the second branch circuit; or the first loading current flows from the first input circuit to the loading stage circuit through the first branch circuit, and the second loading current flows from the first input circuit to the loading stage circuit through the second branch circuit, wherein the loading stage circuit generates the first stage output based on the first loading current and the second loading current. 